张磊  正高级工程师  

研究方向:计算机系统;嵌入式芯片;智能物联网AIoT

所属部门:泛在计算系统研究中心、处理器芯片重点实验室

导师类别:博导计算机系统结构

联系方式:zlei@ict.ac.cn

个人网页:http://people.ucas.edu.cn/~leizhang

简       历:

张磊,博导,正高级工程师,学术百星,青促会会员,中科院科技成果转化特等奖获得者,现任泛在中心物端计算系统实验室执行副主任。万物联网是继PC互联网、移动互联网之后下一个大的信息时代,是我国实现信息基础设施自主可控的历史机遇。张磊博士长期致力于万物联网的芯片和操作系统研发工作,是国内最早推动RISC-V指令系统的学者之一,完成了三代RISC-V芯片研制,在毫瓦级功耗将主流MCU芯片的能效大幅提升,达到国际先进水平。在Web操作系统、人--物交互等方面取得了多项原创性成果,发表在Proceedings of IEEE(影响因子10.69),Transactions on ComputersDAC等国际顶级期刊和会议。2018年创办产业化公司中科物栖,以物端计算机为载体,为海量万物互联应用场景提供低成本、标准化的全栈解决方案,打破端侧功能上限和交互边界,实现真正意义的跨物自由互联。自成立以来得到广泛认可和支持,入选中国最具投资价值企业新芽榜50强和准独角兽。张磊博士入选了2019年《财富》评选的4040岁以下商业精英。 

主要论著:

[1] L. Chao, X. Peng, Z. Xu, L. Zhang, “Ecosystem of Things: Hardware, Software, and Architecture”, Proceedings of the IEEE, 107(8), 2019. (CCF A)
[2] Y. Wang, Y. Han, L. Zhang, H. Li, X. Li, "ProPRAM: Exploiting the Transparent Logic Resources in Non-Volatile Memory for Near Data Computing", ACM/IEEE 52nd Design Automation Conference (DAC), 47-52, July, 2015. (CCF A)
[3] JB. Dong, L. Zhang, YH. Han, Y. Wang, XW. Li, "Wear Rate Leveling: Lifetime Enhancement of PRAM with Endurance Variation", ACM/IEEE 48th Design Automation Conference (DAC), 972-977, Aug. 2011. (CCF A)
[4] Y. Wang, Y. Han, H. Li, L. Zhang, Y. Cheng, X. Li, "PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM", IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 24 (5), pp. 1613-1625, 2016. 
[5] Y. Wang, L. Zhang, Y. Han, H. Li, X. Li, "Data Remapping for Static NUCA in Degradable Chip Multiprocessors", IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 23(5), pp. 879-892, May, 2015. 
[6] Y. Wang, YH. Han, L. Zhang, BZ. Fu, C. Liu, HW. Li, XW. Li, "Economizing TSV Resources in 3-D Network-on-Chip Design", IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 23(3), 493-506, March, 2015. 
[7] Y. Wang, L. Zhang, YH. Han, HW. Li, "Reinventing Memory System Design for Many-Accelerator Architecture", Journal of Computer Science and Technology (JCST), 29 (2), 273-280, Mar. 2014.
[8] P. Chen, L. Zhang, YH. Han, YJ. Chen, "A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications", Journal of Computer Science and Technology (JCST), 29 (2), 239-246, , Mar. 2014.
[9] YQ. Cheng, L. Zhang, YH. Han, XW. Li, "Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs", IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 21(2), 239-249, Feb. 2013.
[10] YQ. Cheng, L. Zhang, YH. Han, XW. Li, "TSV Minimization for Circuit-Partitioned 3D SoC Test Wrapper Design", Journal of Computer Science and Technology (JCST), 28 (1): 119-128, Jan. 2013.
[11] ZW. Xu, XH. Peng, L. Zhang, D. Li, NH. Sun, "The Φ-Stack for Smart Web of Things", ACM/IEEE Symposium on Edge Computing(SEC), 2017.
[12] Y. Wang, L. Zhang, YH. Han, HW. Li, XW. Li, "Flex Memory: Exploiting and Managing Abundant Off-chip Optical Bandwidth", ACM/IEEE Design, Automation and Test in Europe (DATE), 1-6, May 2011. (CCF B)
[13] C. Liu, L. Zhang, YH. Han, XW. Li, "A Resilient On-Chip Router Design Through Data Path Salvaging", ACM/IEEE 16th Asia South Pacific Design Automation Conference (ASP-DAC), March 2011.
[14] C. Liu, L. Zhang, YH. Han, XW. Li, "Vertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip", ACM/IEEE 16th Asia South Pacific Design Automation Conference (ASP-DAC), March 2011.
[15] WW. Chen, Y. Wang, S. Yang, L. Zhang, C. Liu, "You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design", IEEE/ACM Proceedings of Design, Automation and Test in Europe (DATE), 2020.
[16] L. Zhang, Yinhe Han, Qiang Xu, Xiaowei Li and Huawei Li. "On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(9), pp.1173-1186, Sep. 2009.
[17] L. Zhang, Y. Yu, J. Dong, Y. Han, S. Ren, X. Li. "Performance-Asymmetry-Aware Topology Virtualization for Defect-Tolerant NoC-based Many-core Processors", IEEE/ACM Design, Automation and Test in Europe (DATE), pp. 1566-1571, Dresden, Germany, March 8-12, 2010.
[18] L. Zhang, Y. Han, Q. Xu and X. Li. "Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology", IEEE/ACM Design, Automation and Test in Europe (DATE), pp: 891-896, Munich Germany, March 10-14, 2008.

科研项目:

1、国家自然科学基金项目:基于片上网络的众核处理器容错设计方法研究(负责人)
2、国家自然科学基金项目:高效能自适应处理器体系结构关键技术研究(负责人)
3、计算所创新课题:可重塑处理器原理与关键技术研究(负责人)
4、计算所创新课题:物端计算机(负责人)

获奖及荣誉:

2011年,中国质量协会质量技术奖,一等奖
2017年,北京市科学技术奖,二等奖
2019年,中科院科技成果转化奖,特等奖