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Design Challenges in MLC STT-RAM Caches
2014-07-07 | 【 【打印】【关闭】

  时间:201478日(周二)上午10:30-11:30

  地点:计算所4446会议室

   

  摘要

  This presentation will talk about the use of multi-level cell (MLC) spin-transfer torque RAM (STT-RAM) in cache design of microprocessors and embedded systems. By saving two or more digital bits in one storage element, MLC design doubles or even triples the data storage density and hence has been widely adopted in memory technologies. The use of MLC in STT-RAM caches, however, encounters a number of design challenges, including the limited density benefit of the MLC design and the degraded performance and reliability induced by the multi-step accesses. Our latest research outcomes on these topics will be presented and discussed.

   

  主讲人简介

  Hai Li received B.S. and M.S. from Tsinghua University and Ph.D. from Purdue University. She is currently an Assistant Professor in the Department of Electrical and Computer Engineering at University of Pittsburgh. Before joining Pitt in Fall 2012, she has been with Polytechnic Institute of New York University for three years. Prior it, she worked with Qualcomm Inc., Intel Corp., and Seagate Technology. Prof. Li is a recipient of the National Science Foundation (NSF) Early Faculty (CAREER) award, the Defense Advanced Research Projects Agency (DARPA) Young Faculty Award (YFA), and several Best Paper Award and Best Paper Award Nominations at IEEE/ACM conferences. He has published more than 100 research papers in journals and refereed conference proceedings, in the area of EDA, computer architecture, VLSI circuit designs, and embedded systems.

 
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